نوع مقاله : مقاله پژوهشی
نویسندگان
عضو هیات علمی
چکیده
کلیدواژهها
موضوعات
عنوان مقاله [English]
نویسندگان [English]
In this paper, three frequency divider structures for low-power and high-speed applications are proposed. In this design, true single phase clock (TSPC) flip-flop, AND modified gate diffusion input (AND_m-GDI) gate and multiplexer modified gate diffusion input (MUX_m-GDI) gate are used. This technique provides the dividers with reduced power consumption and high speed. Also, these blocks have a good performance at low supply voltage, which has a great effect on power consumption reduction. In order to improve the output swing in m-GDI cells under the mentioned supply voltage, complementary transistors have been used. The ÷2/3, ÷3/4 prescalers and ÷23/24 frequency divider are designed. Finally, according to the techniques used in this paper, a two-level frequency dividers with different values is proposed. The proposed frequency dividers are able to operate to 4 GHz, and their figure-of-merit (FoM) values in compared to other frequency dividers are improved, considerably. The maximum frequencies for the 2/3 and 3/4 are 4.5 GHz and 5 GHz, respectively. Average power consumption at frequency of 2.4 GHz, for the divider 2/3 and 3/4 are equal to 15.25 µW and 16.37 µW, respectively. The FoM values for the proposed frequency dividers in compared to others are considerably improved. Obtained results are based on post layout simulations performed with 65 nm CMOS technology.
کلیدواژهها [English]
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