Hydrophysics

Hydrophysics

Design of Low-Power Divide-by-2/3 Prescaler with m-GDI Method in Fractional-N Frequency Synthesizer for SONAR Application

Document Type : Original Article

Authors
Faculty of Naval Aviation, Malek Ashtar University of Technology, Iran
Abstract
In this paper, three frequency divider structures for low-power and high-speed applications are proposed. In this design, true single phase clock (TSPC) flip-flop, AND modified gate diffusion input (AND_m-GDI) gate and multiplexer modified gate diffusion input (MUX_m-GDI) gate are used. This technique provides the dividers with reduced power consumption and high speed. Also, these blocks have a good performance at low supply voltage, which has a great effect on power consumption reduction. In order to improve the output swing in m-GDI cells under the mentioned supply voltage, complementary transistors have been used. The ÷2/3, ÷3/4 prescalers and ÷23/24 frequency divider are designed. Finally, according to the techniques used in this paper, a two-level frequency dividers with different values is proposed. The proposed frequency dividers are able to operate to 4 GHz, and their figure-of-merit (FoM) values in compared to other frequency dividers are improved, considerably. The maximum frequencies for the 2/3 and 3/4 are 4.5 GHz and 5 GHz, respectively. Average power consumption at frequency of 2.4 GHz, for the divider 2/3 and 3/4 are equal to 15.25 µW and 16.37 µW, respectively. The FoM values for the proposed frequency dividers in compared to others are considerably improved. Obtained results are based on post layout simulations performed with 65 nm CMOS technology.
Keywords

Subjects


  •  

    • Hines P C, Risley W C, O'Connor M P. A wide-band sonar for underwater acoustics measurements in shallow water. In IEEE Oceanic Engineering Society. OCEANS'98. Conference Proceedings (Cat. No. 98CH36259). 1998; 3(1): 1558-1562.
    • Razavi B. RF Microelectronics (Prentice Hall Communication Engineering and Emerging Technologies Series. 2011.
    • Zhen W, Cao S, Su Y, Li S, Jin Z. A novel design method of SOF for InP DHBT ECL and CML static frequency dividers. IEEE Microwave and Wireless Components Letters. 2021; 31(6): 583-586.
    • Waks A, Tesson O, Bellanger M, Taris T, Begueret J B. September. Design of a 5G Application CML Frequency Divider for Improved Efficiency. In 2022 17th European Microwave Integrated Circuits Conference (EuMIC). 2022; 21-24.
    • Jang S L. Current‐reused CMOS 8: 1 injection‐locked frequency divider employing two wide locking range subfrequency dividers. Microwave and Optical Technology Letters. 2023; 65(10): 2716-2720.
    • Krishna M V, Do M A, Yeo K S, Boon C C, Lim W M. Design and analysis of ultra-low power true single phase clock CMOS 2/3 prescaler. IEEE transactions on circuits and systems. 2009; 57(1): 72-82.
    • Hwang Y T, Lin J F. Low voltage and low power divide-by-2/3 counter design using pass transistor logic circuit technique. IEEE transactions on very large scale integration (vlsi) systems. 2011; 20(9): 1738-1742.
    • Jiahui X, Zhigong W, Lu T, Jian X. A 3-GHz dual-modulus prescaler based on improved master-slave DFF. IEEE 12th International Conference on Communication Technology. 2010; 21-24.
    • Xiang H, Wang C, Guo X, Xia Z. Low Voltage and High Speed Dual-Modulus Prescaler with E-TSPC Technology for Frequency Synthesizer. National Academy Science Letters. 2015; 38(3): 207-211.
    • Abiri E, Darabi A. CNTFET-based divide-by-N/[N+ 1] DMFPs using m-GDI method for future generation communication networksNano communication networks.2018; 1-16.
    • Zhu W, Yang H, Gao T, Liu F, Yin T, Zhang D, Zhang H. A 5.8-ghz wideband tspc divide-by-16/17 dual modulus prescaler. IEEE transactions on very large scale integration (VLSI) systems. 2014; 23(1): 194-197.
    • Jiang W, Yu F X. 4.2 GHz 0.81 mW triple-modulus prescaler based on true single-phase clock. Electronics Letters. 2014; 52(12): 1007-1008.
    • Shen T, Liu J, Song C, Xu Z. A High-Speed Low-Power Divide-by-3/4 Prescaler using E-TSPC Logic DFFs. Electronics. 2019; 8(5): 589.
    • Jiang W, Yu F. A novel high-speed divide-by-3/4 prescaler. IEEE Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC). 2016; 479-482.

  • Receive Date 20 December 2023
  • Revise Date 09 January 2024
  • Accept Date 21 January 2024